 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ltc2226h 2226hfa typical a pplica t ion fea t ures a pplica t ions descrip t ion 12-bit, 25msps 125c adc in tqfp the ltc ? 2226h is a 12-bit 25msps, low power 3v a/d converter designed for digitizing high frequency, wide dynamic range signals. the ltc2226h is perfect for demanding imaging and communications applications with ac performance that includes 71.4db snr and 90db sfdr. dc specs include 0.3lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 0.25lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.6v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. typical inl, 2v range sample rate: 25msps C40c to 125c operation single 3v supply (2.8v to 3.5v) low power: 75mw 71.4db snr 90db sfdr no missing codes flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family ltc2246h (14-bit), ltc2226h (12-bit) 32-pin (5mm 5mm) tqfp package automotive industrial wireless and wired broadband communication , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ? + input s/h correction logic output drivers 12-bit pipelined adc core clock/duty cycle control flexible reference d11 ? ? ? d0 clk refh refl a nalog input 2226 ta01 ov dd ognd code 0 inl error (lsb) 3072 2226 ta01b 1024 2048 4096 1.00 0.75 0.50 0.25 0 ? 0.25 ? 0.50 ? 0.75 ? 1.00
ltc2226h 2226hfa con v er t er c harac t eris t ics a bsolu t e maxi m u m r a t ings supply voltage (v dd ) .................................................. 4v digital output ground voltage (ognd) ........ C0.3v to 1v analog input voltage (note 3) ....... C0.3v to (v dd + 0.3v) digital input voltage ...................... C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................. 1500mw operating temperature range ................ C40c to 125c storage temperature range ................... C65c to 150c ov dd = v dd (notes 1, 2) parameter conditions min typ max units resolution (no missing codes) 12 bits integral linearity error differential analog input (note 5) C1.5 0.3 1.5 lsb differential linearity error differential analog input C0.8 0.15 0.8 lsb offset error (note 6) C15 2 15 mv gain error external reference C3 0.5 3 %fs offset drift 10 v/c full-scale drift internal reference 30 ppm/c external reference 5 ppm/c transition noise sense = 1v 0.25 lsb rms the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) p in con f igura t ion 1 2 3 4 5 6 7 8 a in + a in ? gnd refh refl gnd v dd gnd 24 23 22 21 20 19 18 17 d8 d7 d6 ov dd ognd d5 d4 d3 top view lu package 32-lead (5mm 5mm) plastic tqfp 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 clk shdn oe nc nc d0 d1 d2 32 31 30 29 28 27 26 25 v dd v cm sense mode of d11 d10 d9 t jmax = 150c, q ja = 88c/w or d er in f or m a t ion lead free finish tape and reel part marking package description temperature range ltc2226hlu#pbf ltc2226hlu#trpbf 2226h 32-lead (5mm s 5mm) plastic tqpf C40c to 125c lead based finish tape and reel part marking package description temperature range ltc2226hlu ltc2226hlu#tr 2226h 32-lead (5mm s 5mm) plastic tqpf C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ ltc2226h 2226hfa analog inpu t symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 2.8v < v dd < 3.5v (note 7) 0.5v to 1v v v in, cm analog input common mode (a in + + a in C )/2 differential input (note 7) single ended input (note 7) 1 0.5 1.5 1.5 1.9 2 v v i in analog input leakage current 0v < a in + , a in C < v dd C10 10 a i sense sense input leakage 0v < sense < 1v C10 10 a i mode mode pin leakage C10 10 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) d yna m ic accuracy symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 12.5mhz input 70mhz input 69.6 71.4 71.2 70.9 db db db sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 12.5mhz input 70mhz input 74 90 90 85 db db db sfdr spurious free dynamic range 4th harmonic or higher 5mhz input 12.5mhz input 70mhz input 78 90 90 90 db db db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 12.5mhz input 70mhz input 69.1 71.4 71.2 70.8 db db db imd intermodulation distortion f in1 = 4.3mhz, f in2 = 4.6mhz 90 db the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. a in = C1dbfs. (note 4) in t ernal re f erence charac t eris t ics parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/c v cm line regulation 2.8v < v dd < 3.5v 3 mv/v v cm output regulation C1ma < i out < 1ma 4 w t a = 25c. (note 4) d igi t al inpu t s an d d igi t al ou t pu t s symbol parameter conditions min typ max units logic inputs (clk, ` o ` e, shdn) v ih high level input voltage v dd = 3v 2 v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd C10 10 a c in input capacitance (note 7) 3 pf the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) ltc2226h 2226hfa po w er re q uire m en t s symbol parameter conditions min typ max units v dd analog supply voltage (note 9) 2.8 3 3.5 v ov dd output supply voltage (note 9) 0.5 3 3.6 v i vdd supply current 25 30 ma p diss power dissipation 75 90 mw p shdn shutdown power shdn = h, ` o ` e = h, no clk 2 mw p nap nap mode power shdn = h, ` o ` e = l, no clk 15 mw the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 8) t i m ing charac t eris t ics symbol parameter conditions min typ max units f s sampling frequency (note 9) 1 25 mhz t l clk low time duty cycle stabilizer off duty cycle stabilizer on (note 7) 18.9 5 20 20 500 500 ns ns t h clk high time duty cycle stabilizer off duty cycle stabilizer on (note 7) 18.9 5 20 20 500 500 ns ns t ap sample-and-hold aperture delay 0 ns t d clk to data delay c l = 5pf (note 7) 1.4 2.7 6 ns data access time after ` o ` e c l = 5pf (note 7) 4.3 12 ns bus relinquish time (note 7) 3.3 10 ns pipeline latency 5 cycles the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) d igi t al inpu t s an d d igi t al ou t pu t s the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) symbol parameter conditions min typ max units logic outputs ov dd = 3v c oz hi-z output capacitance ` o ` e = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a 2.7 2.995 2.99 v v v ol low level output voltage i o = 10a i o = 1.6ma 0.005 0.09 0.4 v v ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v ltc2226h 2226hfa frequency (mhz) 0 amplitude (db) 2226 g04 2 4 6 8 10 12 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 frequency (mhz) 0 amplitude (db) 2226 g06 2 4 6 8 10 12 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 frequency (mhz) 0 amplitude (db) 2226 g05 2 4 6 8 10 12 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 2227 g1 3 2227 g1 4 2227 g1 5 code 0 inl error (lsb) 3072 2226 g01 1024 2048 4096 1.00 0.75 0.50 0.25 0 ? 0.25 ? 0.50 ? 0.75 ? 1.00 code 0 dnl error (lsb) 3072 2226 g02 1024 2048 4096 1.00 0.75 0.50 0.25 0 ? 0.25 ? 0.50 ? 0.75 ? 1.00 frequency (mhz) 0 amplitude (db) 2226 g03 2 4 6 8 10 12 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 25mhz, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C0.5 lsb when the output code fickers between 0000 0000 0000 and 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 25mhz, input range = 1v p-p with differential drive. note 9: recommended operating conditions. tpical p er f or m ance c harac t eris t ics typical inl, 2v range, 25msps typical dnl, 2v range, 25msps 8192 point fft, f in = 5mhz, C1db, 2v range, 25msps 8192 point fft, f in = 30mhz, C1db, 2v range, 25msps 8192 point fft, f in = 70mhz, C1db, 2v range, 25msps 8192 point fft, f in = 140mhz, C1db, 2v range, 25msps ltc2226h 2226hfa input level (dbfs) ?60 ?50 ? 4 0 ?20 ?30 ?10 0 sfdr (dbc and dbfs) 2226 g1 3 120 110 100 90 80 70 60 50 40 30 20 sample rate (msps) 0 35 30 25 20 15 30 2226 g1 4 10 20 25 5 1 5 3 5 i vdd (ma) sample rate (msps) i ovdd (ma) 2226 g1 5 3 2 1 0 0 20 30 5 1 5 35 10 25 dbfs dbc 90dbc sfdr reference line 2v range 1v range input frequency (mhz) 0 100 95 90 85 80 75 70 65 150 2226 g1 0 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110 100 90 80 70 60 40 50 2226 g1 1 10 20 30 input level (dbfs) ?60 ?50 snr (dbc and dbfs) ? 4 0 ?20 ?30 ?10 0 2227 g1 2 80 70 60 50 40 30 20 10 0 snr sfdr dbfs dbc frequency (mhz) 0 amplitude (db) 2226 g07 2 4 6 8 10 12 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 code count 2050 2226 g08 2048 2049 70000 60000 50000 40000 30000 20000 10000 0 61758 1607 2155 input frequency (mhz) 0 snr (dbfs) 70 71 200 2226 g09 69 68 50 100 150 72 typical p er f or m ance c harac t eris t ics p t fft in mh mh b v r m g i h m snr i f b v r m sfdr i f b v r m snr sfdr s r v r in mh b snr i l in mh v r b sfdr i l in mh v r m i vdd s r mh s w i b i ovdd s r mh s w i b o vdd v ltc2226h 2226hfa p in func t ions a in + (pin 1): positive differential analog input. a in - (pin 2): negative differential analog input. gnd (pins 3, 6, 8): adc power ground. refh (pin 4): adc high reference. bypass to pin 5 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pin 5 with an additional 2.2f ceramic chip capacitor and to gnd with a 1f ceramic chip capacitor. refl (pin 5): adc low reference. bypass to pin 4 with a 0.1f ceramic chip capacitor as close to the pin as possible. also bypass to pin 4 with an additional 2.2f ceramic chip capacitor and to ground with a 1f ceramic chip capacitor. v dd (pins 7, 32): 3v supply. bypass to gnd with 0.1f ceramic chip capacitors. clk (pin 9): clock input. the input sample starts on the positive edge. shdn (pin 10): shutdown mode selection pin. connecting shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. if the clock duty cycle stabilizer is used, a >1s high pulse should be applied to the shdn pin once the power supplies are stable at power up. oe (pin 11): output enable pin. refer to shdn pin func - tion. nc (pins 12, 13): do not connect these pins. d0 C d11 (pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): digital outputs. d11 is the msb. ognd (pin 20): output driver ground. ov dd (pin 21): positive supply for the output drivers. bypass to ground with 0.1f ceramic chip capacitor. of (pin 28): over/under flow output. high when an over or under fow has occurred. mode (pin 29): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin 30): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 31): 1.5v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. ltc2226h 2226hfa f unc t ional bloc k d iagra m shift register and correction diff ref amp ref buf 2.2 f 1 f 1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 2226 f01 input s/h sense v cm a in ? a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d11 d0 ? ? ? figure 1. functional block diagram t i m ing d iagra m t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ? 4 n ? 3 n ? 2 n ? 1 clk d0-d11, of 2226 td01 n ? 5 n ltc2226h 2226hfa dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamen - tal input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the frst fve harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ((v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1) where v1 is the rms amplitude of the fundamental fre - quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the ffth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are ap - plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodula - tion distortion is defned as the ratio of the rms value of a pplica t ions i n f or m a t ion either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spuri - ous noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) converter operation as shown in figure 1, the ltc2226h is a cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value fve cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2226h has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifer. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplifed and ltc2226h 0 2226hfa a pplica t ions i n f or m a t ion output by the residue amplifer. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifer which drives the frst pipelined adc stage. the frst stage acquires the output of the s/h dur - ing this high phase of clk. when clk goes back low, the frst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and ffth stages, resulting in a ffth stage residue that is sent to the sixth stage adc for fnal evaluation. each adc stage following the frst has additional range to accommodate fash and amplifer offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2226h cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, v dd v dd 15 ? 15 ? c parasitic 1pf c parasitic 1pf c sample 4pf c sample 4pf ltc2226h a in + a in ? clk 2226 f02 figure 2. equivalent input circuit the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har - monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in C should be connected to v cm or a low noise reference voltage between 1v and 1.5v. common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin (pin 31) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2f or greater capacitor. ltc2226h 2226hfa input drive impedance as with all high performance, high speed adcs, the dy - namic performance of the ltc2226h can be infuenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can infuence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 w or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2226h being driven by an rf transformer with a center tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the trans - former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 w for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential amplifer to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the sfdr at high input frequencies. figure 5 shows a single-ended input circuit. the impedance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. the 25 w resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. a pplica t ions i n f or m a t ion 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in ? 12pf 2.2 f v cm ltc2226h analog input 0.1 f t 1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 2226 f03 figure 3. single-ended to differential conversion using a transformer 25 ? 25 ? 12pf 2.2 f v cm ltc2226h 2226 f04 ? ? + + cm analog input high speed differential amplifier a in + a in ? 25 ? 0.1 f analog input v cm a in + a in ? 1k 12pf 2226 f05 2.2 f 1k 25 ? 0.1 f ltc2226h figure 4. differential drive with an amplifer figure 5. single-ended drive ltc2226h 2226hfa reference operation figure 6 shows the ltc2226h reference circuitry consist - ing of a 1.5v bandgap reference, a difference amplifer and switching and control circuit. the internal voltage reference can be confgured for two pin selectable input ranges of 2v (1v differential) or 1v (0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifer to gener - ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifer generates the high and low reference for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in figure 7. an external reference can be used by apply - ing its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1f ceramic capacitor. input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise performance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 3.8db. a pplica t ions i n f or m a t ion v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ? v sense for 0.5v < v sense < 1v 1.5v refl 2.2 f 2.2 f internal adc high reference buffer 0.1 f 2226 f06 ltc2226h 4 ? diff amp 1 f 1 f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control figure 6. equivalent reference circuit v cm sense 1.5v 0.75v 2.2 f 12k 1 f 12k 2226 f07 ltc2226h clk 100 ? 0.1 f 4.7 f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 2226 f08 ltc2226h figure 7. 1.5v range adc figure 8. clk drive using an lvds or pecl to cmos converter ltc2226h 2226hfa driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a differential clock can also be used along with a low-jitter cmos converter before the clk pin (see figure 8). the noise performance of the ltc2226h can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. maximum and minimum conversion rates the maximum conversion rate for the ltc2226h is 25msps. for the adc to operate properly, the clk signal should have a 50% (5%) duty cycle. each half cycle must have at least 18.9ns for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. if the clock duty cycle stabilizer is used, a >1s high pulse should be applied to the shdn pin once the power supplies are stable at power up. the lower limit of the ltc2226h sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specifed minimum operating frequency for the ltc2226h is 1msps. digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits, and the overfow bit. digital output buffers figure 9 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 w to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2226h should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. a pplica t ions i n f or m a t ion table 1. output codes vs input voltage a in + C a in C (2v range) of d11 C d0 (offset binary) d11 C d0 (2s complement) >+1.000000v +0.999512v +0.999024v 1 0 0 11 11 1111 1111 11 11 1111 1111 11 11 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488v 0.000000v C0.000488v C0.000976v 0 0 0 0 10 00 0000 0001 10 00 0000 0000 01 11 1111 1111 01 11 1111 1110 00 00 0000 0001 00 00 0000 0000 11 11 1111 1111 11 11 1111 1110 C0.999512v C1.000000v ltc2226h 2226hfa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ac k age descrip t ion lu32 tqfp 0906 rev? 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 7.00 bsc a a 5.00 bsc 1 2 3 5.00 bsc 7.00 bsc 32 1.20 max 0.95 ? 1.05 0.05 ? 0.15 0.09 ? 0.22 0.50 bsc 0.17 ? 0.27 gauge plane 0.25 note: 1. drawing conforms to jedec #ms-026 package outline 2. dimensions are in millimeters 3. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 4. pin-1 indentifier is a molded indentation 5. exact shape of each corner is optional 6. drawing is not to scale see note: 4 see note: 5 r0.08 ? 0.20 5.15 ? 5.25 3.50 ref 1 2 3 3.50 ref 5.15 ? 5.25 32 package outline recommended solder pad layout apply solder mask to areas that are not soldered section a ? a 0.50 bsc 0.22 ? 0.30 1.30 min lu package 32-lead plastic tqfp (5mm 5mm) (reference ltc dwg # 05-08-1735 rev ?) ltc2226h 2226hfa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0507 rev a ? printed in usa r ela t e d p ar t s part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt1993-2 high speed differential op amp 800mhz bw, C70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/output amplifer/driver low distortion: C94dbc at 1mhz ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2225 12-bit, 10msps, 3v adc, lowest power 60mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2226 12-bit, 25msps, 3v adc, lowest power 75mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2227 12-bit, 40msps, 3v adc, lowest power 120mw, 71.4db snr, 90db sfdr, 32-pin qfn ltc2228 12-bit, 65msps, 3v adc, lowest power 205mw, 71.3db snr, 90db sfdr, 32-pin qfn ltc2229 12-bit, 80msps, 3v adc, lowest power 211mw, 70.6db snr, 90db sfdr, 32-pin qfn ltc2236 10-bit, 25msps, 3v adc, lowest power 75mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2237 10-bit, 40msps, 3v adc, lowest power 120mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2238 10-bit, 65msps, 3v adc, lowest power 205mw, 61.8db snr, 85db sfdr, 32-pin qfn ltc2239 10-bit, 80msps, 3v adc, lowest power 211mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2245 14-bit, 10msps, 3v adc, lowest power 60mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2246 14-bit, 25msps, 3v adc, lowest power 75mw, 74.5db snr, 90db sfdr, 32-pin qfn ltc2247 14-bit, 40msps, 3v adc, lowest power 120mw, 74.4db snr, 90db sfdr, 32-pin qfn ltc2248 14-bit, 65msps, 3v adc, lowest power 205mw, 74.3db snr, 90db sfdr, 32-pin qfn ltc2249 14-bit, 80msps, 3v adc, lowest power 222mw, 73db snr, 90db sfdr, 32-pin qfn ltc2250 10-bit, 105msps, 3v adc, lowest power 320mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2251 10-bit, 125msps, 3v adc, lowest power 395mw, 61.6db snr, 85db sfdr, 32-pin qfn ltc2252 12-bit, 105msps, 3v adc, lowest power 320mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2253 12-bit, 125msps, 3v adc, lowest power 395mw, 70.2db snr, 88db sfdr, 32-pin qfn ltc2254 14-bit, 105msps, 3v adc, lowest power 320mw, 72.4db snr, 88db sfdr, 32-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifer/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 w single-ended rf and lo ports |
Price & Availability of LTC2226HLUTRPBF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |